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Overview

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This course introduces basics of CMOS VLSI design and modeling of digital circuits and systems.

Teaching Load (Spring 2017):

• Lectures (3 hours), Tutorials (2 hours), Lab (2 hours)
• Office Hours: Saturday from 10:30AM to12:00PM.
• Teaching Assistant: Eng. Mohamed Megahed

Course work and assesment (out of 125) are as follows:

• 4 Labs (10 marks) + Attendance (5 marks)
• 1 Project (10 marks): The project desription file [PDF]
•  Midterm exam (25 marks)
•  Final Exam (75 marks)

• VLSI Implementation Strategies.
• MOSFET non ideal characteristics.
• Delay models and logical effort.
• Power consumption and low-power design considerations.
• Interconnect modeling, impact, and engineering.
• Robustness: Variability, Reliability, and Scaling.
• Design Methodologies and Tools.
• Testing, Debugging, and Verification.

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Resources

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• Textbooks:
  • “CMOS VLSI Design A Circuits and Systems Perspective”, Neil Weste, David Harris.
Reference books:
• "Top-down Digital VLSI Design: From Architectures to Gate-level Circuits and FPGAs".Hubert Kaeslin, 2014.
• “Digital integrated circuits 2nd ed.” Rabaey, Jan M., Anantha P. Chandrakasan, and Borivoje Nikolic., (2002).

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Course Materials

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Lecture 1	Syllabus & Introduction	[PDF] [PDF]
Lecture 2	Digital IC Review MIPS Processor Design	[PDF] [PDF]
Lectures 3, 4	MOSFET Review MOSFET Non-Ideal Effects	[PDF] [PDF]
Lecture 5	Delay Analysis	[PDF]
Lecture 6	Logical Effort	[PDF]
Lecture 7	Power	[PDF]
Lecture 8	Wires	[PDF]
Lectures 9-12	From Algorithms to Architectures	[PDF]
Lecture 13-17	Circuit Modeling with HDLs	[PDF]

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Sheet 1	Delay	[PDF]
Sheet 2	Power	[PDF]
Sheet 3	Interconnect	[PDF]
Sheet 4	From Algorithms to Architectures	[PDF]
Sheet 5	Circuit Modeling with HDLs	[PDF]

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Lab 1	Cell Design and Verification	[PDF]
Lab 2	Datapath Design and Verification	[PDF]
Lab 3	Controller Design and Verification	[PDF]
Lab 4	Full Chip Assembly	[PDF]
Project	CMOS VLSI Design	[PDF]