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Electrical Engineering Department
Faculty of Engineering
Alexandria University
EE432: VLSI Modeling and Design
Lecturer: Dr. Mohammed Morsy Farag
Overview
This course introduces basics of CMOS VLSI
design and modeling of digital circuits and systems. Course objectives
include:
- Describe the digital VLSI design flow
including both top-down and bottom-up approaches.
- Design and analyze digital VLSI chips
using CMOS technology.
- Introduce basic concepts of CMOS VLSI
design, layout, and fabrication.
- Understand RTL design guidelines.
- Learn to use HDLs to capture VLSI
circuits and systems.
- Introduce transformations from
algorithms to VLSI architectures.
- Describe general VLSI system
components including combinational and sequential logic gates,
arithmetic circuits, and memory elements.
- Learn to use physical layout tools to
design and simulate basic combinational and sequential logic
circuits.
- Learn to use Verilog to design complex
digital circuits, using simulators and synthesis tools:
- Structural, Dataflow, Behavioral
Design.
- Test-bench Design and Digital
Simulation.
- Design of Combinational &
Sequential artifacts.
- Digital Synthesis using tools.
Teaching Load (Spring 2014):
- Lectures (3 hours), Tutorials (2 hours), Lab (2 hours)
- Office Hours: Saturday from 10:30AM to12:00PM.
- Teaching Assistant:
Eng. Mohamed Megahed
Course work and assesment (out of 125) are as follows:
- 6 Labs (10 marks) +
Attendance (5 marks)
- 2 Projects (10 marks)
- Layout Project: Read this file [PDF] for the project details
and important dates.
- Verilog HDL Project: Read this file [PDF] for the project
details and important dates.
- A Midterm exam (25 marks)
- A Final Exam (75 marks)
- CMOS VLSI circuits modeling and design.
- CMOS VLSI layout and fabrication.
- Physical layout
software.
- Layout design and
simulation Labs and project.
- Midterm Exam.
- VLSI systems
design using Verilog HDL.
- RTL design
guidelines.
- HDL simulation and
synthesis labs and project.
- Final exam
Resources
- Textbooks:
- “INTRODUCTION TO VLSI CIRCUITS AND
SYSTEMS”, John P. Uyemura.
- “Verilog HDL A Guide to Digital
Design and Synthesis”, Samir Palnitkar.
- Reference books:
- “CMOS VLSI Design A Circuits
and Systems Perspective”, Neil Weste, David Harris.
- “Digital Integrated Circuit Design
From VLSI Architectures to CMOS Fabrication”, Hubert Kaeslin.
Course Materials
Lectures
Lecture 1 |
Introcuction
to VLSI and Digital IC |
[PDF],[PDF] |
Lecture 2,3 |
Physical Structures of CMOS ICs |
[PDF] |
Lecture 4 |
Fabrication of CMOS ICs |
[PDF] |
Lecture 5 |
Elements of Physical Design |
[PDF] |
Lecture 6 |
Digital Layout IC Mask Design
Standard Cell Techniques IC Mask Design
|
[PDF]
[PDF] |
Lecture 7-10 |
System Specifications Using Verilog HDL |
[PDF] |
Lecture 11 |
General VLSI System Components |
[PDF] |
Lecture 12 |
Arithmetic Circuits in CMOS VLSI |
[PDF] |
Lecture 13 |
Memory and Programmable Logic |
[PDF] |
Lecture 14 |
VLSI Clocking and System Design |
[PDF] |
Sheets
Sheet 1 |
CMOS IC Layout and Design Rules (1) |
[PDF] |
Sheet 2 |
CMOS IC Layout and Design Rules (2) |
[PDF] |
Sheet 3 |
CMOS IC Layout and Design Rules (3) |
[PDF] |
Sheet 4 |
Verilog HDL (Palnitkar Book Problems) |
[PDF] |
Sheet 5 |
Verilog HDL (Behavioral Modeling) |
[PDF] |
Sheet 6 |
Verilog HDL (Additional Problems) |
[PDF] |
Lab Assignments
Lab 1 |
Physical Design and Layout of A CMOS
Inverter |
[PDF] |
Lab 2 |
Physical Design of a 2-to-1 MUX and XOR |
[PDF] |
Lab 3 |
Hierarchial Design and Layout of Complex Logic Circuits |
[PDF] |
Lab 4 |
System-Level Design of Combinational Circuits |
[PDF] |
Lab 5 |
System-Level Design of Sequential Circuits |
[PDF] |
Lab 6 |
System-Level Design of Finite State Machines |
[PDF] |
© Copyright 2010-2017, Mohammed M. Farag | Last updated: February 24, 2017