
This course introduces basics and fundamentals of digital integrated circuits and particularly CMOS circuits. Course objectives include:
Teaching Load (Spring 2016):
Course work and assesment (out of 100) are as follows:
Project: 10 marks
A Midterm exam: 25 marks
A Final Exam: 75 marks
CAD Tools to be used are:
| Lecture 1 | Syllabus and Introcuction | [PDF] , [PDF] |
| Lecture 2 | MOSFET Layout and Fabrication | [PDF] |
| Lecture 3 | MOSFET Operation and Scaling Effects |
[PDF], [PDF] |
| Lecture 4 | MOSFET Modeling in Spice | [PDF] |
| Lecture 5 | MOSFET Inverter Static Characteristics | [PDF] |
| Lecture 6 | MOS Inverter Dynamic Characteristics | [PDF] |
| Lecture 7 | Interconnect Analysis | [PDF] |
| Lecture 8 | Combinational Logic Circuits | [PDF] |
| Lecture 9 | Sequential Logic Circuits | [PDF] |
| Lecture 10 | Semiconductor Memories | [PDF] |
| Sheet 1 | MOSFET Inverter Static Characteristics | [PDF] |
| Sheet 2 | CMOS Inverter Dynamic Characteristics | [PDF] |
| Sheet 3 | Layout of CMOS ICs | [PDF] |
| Sheet 4 | Combinational Logic Circuits | [PDF] |
| Sheet 5 | Sequential MOS Logic Circuits | [PDF] |
| Sheet 6 | Semiconductor Memories | [PDF] |
| Guide to Tanner EDA | [PDF] | |
| Lab 1 | CMOS Inverter Layout | [PDF] |
| Lab 2 | Static and Dynamic Characteristics of CMOS Inverter | [PDF] |
| Lab 3 | CMOS Combinational Logic Gates | [PDF] |
| Mid-term Exams | 2016 |
| Final Exams | 2016 |